1. Field of the Invention
The present invention relates to a detecting of a wobble signal on an optical recording medium and using the wobble signal to correct an error thereof, and more particularly, to an apparatus which detects an error in a wobble signal on an optical recording medium using a window signal and corrects the wobble error, and a phase locked loop (PLL) circuit using the apparatus.
2. Description of the Related Art
Generally, a phase locked loop (PLL) circuit is used to generate a system clock from a wobble signal when reproducing data on an optical recording medium such as a CD and a DVD-ROM.
Tracks of concentric circles are formed on a surface of a recordable optical recording medium such as a CD-R, a CD-RW, and a DVD-RAM, so as to write data to the surface thereof. To record data at a desired position of the surface of such a disc, it is required to follow a target track of the disc on which data is to be recorded and record the data on the track. To follow the target track, operations to detect a position of a pickup on the disc are needed, and a wobble signal, which is a single frequency signal, is formed on the surface of the disc to be used during the detecting operations.
FIG. 1 shows a partial diagram of tracks of an optical recording medium, i.e., a DVD-RAM. Referring to FIG. 1, wobble signals and a header information signal are recorded along the tracks. A header, in which information regarding the position of the disc is recorded according to predetermined rules, is interleaved with the wobble signals. The position or address of the disc can be detected using the information recorded in the header.
FIG. 2 shows a block diagram of a conventional system clock generator which generates a clock signal using a wobble signal on the optical recording medium shown in FIG. 1. The system clock generator includes a preprocessor 200, a phase frequency detector (PFD) 210, a loop filter 220, a voltage controlled oscillator (VCO) 230, and a frequency divider 240.
The preprocessor 200 reads the wobble signal from the optical recording medium 20 using an optical pickup (not shown), binarizes the wobble signal, and outputs the binarized wobble signal as a raw wobble signal (rwb).
The PFD 210 compares the binarized wobble signal output from the preprocessor 200 with a phase locked wobble signal and outputs a difference therebetween.
The loop filter 220 filters an output of the PFD 210 to output a stable control voltage signal.
The VCO 230 generates an oscillation signal of frequency that is proportional to that of the voltage signal output from the loop filter 220 and outputs the oscillation signal. The oscillation signal acts as a system clock signal.
The frequency divider 240 divides a frequency of the system clock signal output from the VCO 230 to a predetermined frequency of the system clock signal and outputs the result as a phase locked wobble signal (pwb).
The system clock generator of FIG. 2 is a representative example of a PLL circuit that is required to perform writing and reading operations using a wobble signal on an optical recording medium, in synchronization with a binarized rwb signal.
FIGS. 3A-3C are timing diagrams of signals to illustrate an operation of the PFD 210 of FIG. 2. FIGS. 3A and 3B denote a raw wobble signal (rwb) and a phase locked wobble signal (pwb) input to the PFD 210, respectively. FIG. 3C denotes a signal, output from the PFD 210, which is a voltage signal that represents a difference of phase between the signals rwb and pwb.
As shown in FIGS. 3A-3C, the PFD 210 detects rising edges of the signals rwb and pwb and outputs a phase difference between these signals as a voltage signal that changes at three levels: a level of high voltage VOH, a level of low voltage VOL, and a level of high impedance Hi-Z. In most cases, the PFD 210 operates normally but it may not operate properly due to noise, such as a glitch, input to the PFD 210.
FIGS. 4A-4D are timing diagrams of signals to illustrate a mis-operation of the PFD 210 of FIG. 2. FIGS. 4A and 4B denote an input raw wobble signal (rwb) and an input phase locked wobble signal (pwb), respectively. The rwb signal may include a glitch signal generated due to physical defects of an optical recording medium. FIG. 4C denotes an actual voltage signal output from the PFD 210, which is a measure of the phase difference between the signals rwb and pwb. FIG. 4D denotes a desired signal output from the PFD 210 not in consideration of the glitch in the rwb signal.
Where the PFD 210 malfunctions to output the signal of FIG. 4C due to the glitch contained in the rwb signal, it is impossible to stop the PFD 210 from malfunctioning. The malfunction of the PFD 210 may result in generation of an abnormal system clock and may make it difficult to perform the writing and reading operations on an optical recording medium.